module regfile(
    input         clk,
    input         rst,
    // READ PORT 1
    input  [ 4:0] raddr0,
    output [31:0] rdata0,
    // READ PORT 2
    input  [ 4:0] raddr1,
    output [31:0] rdata1,
    // WRITE PORT
    input         we,       //write enable, HIGH valid
    input  [ 4:0] waddr,
    input  [31:0] wdata
);
reg [31:0] rf[31:0];

//WRITE
`ifdef RUN_SIM
integer i;
always @(posedge clk) begin
    for (i = 0; i < 32; i = i + 1) begin
        if (rst) begin
            rf[i]<= 32'd0;
        end else if (we && i == waddr) begin
            rf[i]<= wdata;
        end
    end
end
`else
always @(posedge clk) begin
    if (we) rf[waddr] <= wdata;
end
`endif

//READ OUT 1
assign rdata0 = (raddr0 == 5'b0) ? 32'b0 : rf[raddr0];

//READ OUT 2
assign rdata1 = (raddr1 == 5'b0) ? 32'b0 : rf[raddr1];

endmodule